I am a Ph.D. graduate student in Computer Scinece, advised by Prof. Kevin Skadron.
LU Decomposition (LUD) on CUDA
This is part of the Rodinia benchmark suite for GPGPU computing.
Dark Silicon and Heterogeneous Architectures
We have developed a analytical framework, called Lumos, to explore design spaces of heterogeneous architectures composed of conventional cores, reconfigurable logic (both fine-grained such as FPGA and coarse-grained such as Dyser), and dedicated ASICs.
- L. Wang, R. Bertran, M. S. Gupta, A. Buyuktosunoglu, P. Bose, K. Skadron, "Characterization of Transient Error Tolerance for a Class of Mobile Embedded Applications." In Proceedings of IEEE International Symposium on Workload Characterization, 2014 (IISWC 2014).
- L. Wang, J. A. Rivers, M. S. Gupta, A. J. Vega, A. Buyuktosunoglu, P. Bose, K. Skadron, "Resilience and Real-Time Constrained Energy Optimization in Embedded Processor Systems." In Proceeding of 10th Workshop on Silicon Errors in Logic-System Effects (SELSE '14).
- L. Wang, K. Skadron, "Implications of the Power Wall: Dim Cores and Reconfigurable Logic." IEEE MICRO, Sep.-Oct. 2013.
- L. Wang, K. Skadron, "Dark vs. Dim Silicon and Near-Threshold Computing Extended Results." Technical Report UVA-CS-2013-01, Department of Computer Science, University of Virginia, 2013. [pdf]
- L. Wang, K. Skadron, B. H. Calhoun, "Dark vs. Dim Silicon and Near-Threshold Computing." In the first Workshop of Dark Silicon, in conjunction of ISCA 2012 (DaSi 2012).
- S. Che, J. W. Sheaffer, M. Boyer, L. G. Szafaryn, L. Wang, and K. Skadron, "A Characterization of the Rodinia Benchmark Suite with Comparison to Contemporary CMP Workloads." In Proceedings of the IEEE International Symposium on Workload Characterization, 2010 (IISWC 2010).
- A collection of various tool tips can be found at here
- A Python-based many-core performance evaluation framework, Lumos
